With the growing complexity of today’s designs, designers need to analyze their logic structures pre-layout, using a technique known as static timing analysis. The Designer software toolset includes Static Timer (ST), a powerful and integrated front-end timing analyzer that can be run either pre-layout or post-layout.Because the ST approach provides a direct representation of the timing constraints, it tends to be significantly more efficient than gate-level simulation, which is tightly bound to the layout and DPI includes the static timing analysis tool called Timer. The timing information is accessible after compiling the design netlist in our application. However, the final and accurate timing information will be available after place-and-route

Input Required for STA

• Netlist
• .lib for standard cells
• .lib for hard macros
• SPEF/SDF files
• Constraints files (.sdc)

• Analysis Modes
• Data to Data Checks 
• Case Analysis 
• Multiple Clocks per Register 
• Minimum Pulse Width Checks 
• Derived Clocks 
• Clock Gating Checks 
• Netlist Editing 
• Report_clock_timing 
• Clock Reconvergence Pessimism 
• Worst-Arrival Slew Propagation
• Debugging Delay Calculation 

• Quick Timing Model (QTM)  
• Extracted Timing Model (ETM)
•  Interface Logic Model (ILM)  
• Stamp Model